test(encode/nvenc): the NVIDIA HDR leg, verified on an RTX 5070 Ti
The NVIDIA half of "zero-copy, no host CSC, 10-bit HDR" had never met a GPU. Two `#[ignore]`d smokes now drive it, run on `.41` (Bazzite f43, RTX 5070 Ti, driver 595.58.03): * `nvenc_cuda_hdr10_packed_rgb` — a packed 2:10:10:10 CUDA payload straight into NVENC as `ARGB10`, HEVC **and** AV1. Asserts what would catch a mislabelled stream: the encoder DERIVED 10-bit and HDR from the input format rather than being told, and picked `ARGB10` for `X2Rgb10`. That derivation is what selects Main10 / AV1-at-10 and the BT.2020 PQ signalling. * `nvenc_cuda_hdr10_cursor_blend` — `cursor_blend.comp` MODE 3/4, the 10-bit channel-unpacking twin. Asserts the blend targets `SlotFormat::X2Rgb10` and not the 8-bit layout, which would tint the pointer and shift its channels. Both green, and the dumped bitstreams decode 0-error reporting `Main 10` / AV1 `Main`, `yuv420p10le`, `bt2020nc` / `smpte2084` / `bt2020`. There is no host colour conversion anywhere on this path: the frame arrives as a LINEAR dmabuf, crosses to CUDA through the Vulkan bridge, and NVENC's ASIC does the BT.2020 conversion following the VUI the session configured. The "no CSC" property AMD gets from the EFC, NVIDIA gets from the encoder itself. The whole pre-existing `nvenc_` suite was re-run alongside them — 16/16, no regression from the depth-derivation and buffer-format changes underneath it. Capture half checked too: the patched gamescope binary built on the AMD box runs unmodified on the NVIDIA one (same Fedora 43 base) and its node offers the same four formats with the colorimetry props — so headless gamescope + 10-bit PQ is not AMD-specific.
This commit is contained in:
@@ -2609,6 +2609,172 @@ mod tests {
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);
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}
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/// A packed 2:10:10:10 (`X2Rgb10`) CUDA frame — the layout an HDR gamescope capture imports
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/// through the Vulkan bridge, and what NVENC ingests as `ARGB10` with no host CSC at all.
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/// The device memory is uninitialised: this smoke asserts the session/registration/encode
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/// machinery, not picture fidelity (that is the AMD round-trip's job — the CSC here is
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/// NVENC's own ASIC, not our shader).
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fn rgb10_frame(w: u32, h: u32, i: u32) -> CapturedFrame {
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let buf = DeviceBuffer::alloc(w, h).expect("alloc packed RGB device buffer");
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CapturedFrame {
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width: w,
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height: h,
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pts_ns: i as u64 * 16_666_667,
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format: PixelFormat::X2Rgb10,
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payload: FramePayload::Cuda(buf),
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cursor: None,
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}
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}
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/// ON-HARDWARE: the HDR path — a packed 10-bit PQ/BT.2020 CUDA payload straight into NVENC as
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/// `ARGB10`, which is what makes an NVIDIA HDR session zero-copy AND host-CSC-free: NVENC does
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/// the BT.2020 conversion in the ASIC, following the VUI this session configures.
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///
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/// The load-bearing assertions are the ones that would catch a mislabelled stream: the encoder
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/// must have DERIVED 10-bit from the input format (not merely been asked for it), and it must
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/// report HDR — that pair is what selects Main10 / AV1-10 and the BT.2020 PQ signalling.
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#[test]
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#[ignore = "requires an NVIDIA GPU + driver with 10-bit encode"]
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fn nvenc_cuda_hdr10_packed_rgb() {
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for codec in [Codec::H265, Codec::Av1] {
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const W: u32 = 1280;
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const H: u32 = 720;
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pf_zerocopy::cuda::make_current().expect("shared CUDA context current");
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let mut enc = NvencCudaEncoder::open(
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codec,
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PixelFormat::X2Rgb10,
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W,
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H,
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60,
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20_000_000,
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true,
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10,
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ChromaFormat::Yuv420,
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false,
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)
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.expect("open NVENC CUDA session");
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let mut aus = 0usize;
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let mut first_key = false;
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let mut stream: Vec<u8> = Vec::new();
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for i in 0..4u32 {
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enc.submit_indexed(&rgb10_frame(W, H, i), i)
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.expect("submit");
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while let Some(au) = enc.poll().expect("poll") {
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if aus == 0 {
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first_key = au.keyframe;
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}
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assert!(!au.data.is_empty(), "empty AU");
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stream.extend_from_slice(&au.data);
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aus += 1;
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}
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}
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enc.flush().ok();
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// Dumped for the out-of-band ffprobe check. In-tree we can assert the encoder's OWN
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// view of the config; only a decoder confirms the BITSTREAM says Main10 / BT.2020 /
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// PQ, which is what a client actually reads.
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if let Ok(home) = std::env::var("HOME") {
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let ext = if codec == Codec::Av1 { "obu" } else { "h265" };
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let path = format!("{home}/nvenc-hdr10.{ext}");
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if std::fs::write(&path, &stream).is_ok() {
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println!(
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"nvenc_cuda HDR10 {codec:?}: wrote {path} ({} bytes)",
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stream.len()
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);
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}
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}
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assert!(aus > 0, "{codec:?}: no AUs produced");
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assert!(first_key, "{codec:?}: first AU must be the session IDR");
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// The whole point: depth + HDR came from the INPUT format, so the bitstream's profile
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// and colour signalling describe what was actually encoded.
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assert_eq!(enc.bit_depth, 10, "{codec:?}: must have derived 10-bit");
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assert!(
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enc.hdr,
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"{codec:?}: must have derived HDR from the PQ format"
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);
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assert_eq!(
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enc.buffer_fmt,
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nv::NV_ENC_BUFFER_FORMAT::NV_ENC_BUFFER_FORMAT_ARGB10,
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"{codec:?}: X2Rgb10 must ingest as ARGB10"
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);
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println!("nvenc_cuda HDR10 {codec:?}: {aus} AUs, ARGB10 in, 10-bit derived");
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}
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}
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/// ON-HARDWARE: the cursor blended into a **10-bit** input surface — `cursor_blend.comp`'s
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/// MODE 3/4, which unpack 2:10:10:10 channels instead of bytes. New shader code, and the only
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/// way a gamescope pointer reaches an HDR NVIDIA stream: the packed-RGB slot is what NVENC
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/// ingests, so the blend has to happen in that layout rather than in a YUV plane.
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///
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/// Asserts the machinery — AUs come out, and the blend targets the 10-bit slot layout rather
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/// than silently falling back to the 8-bit one, which would tint the pointer and shift its
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/// channels. Blend CORRECTNESS is display-referred by design (see the shader), so it is
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/// judged by eye on a dump, not here.
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#[test]
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#[ignore = "requires an NVIDIA GPU + driver with 10-bit encode"]
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fn nvenc_cuda_hdr10_cursor_blend() {
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const W: u32 = 1280;
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const H: u32 = 720;
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pf_zerocopy::cuda::make_current().expect("shared CUDA context current");
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if !stream_ordered_requested() || async_retrieve_requested() {
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println!("skipped: stream-ordered submit disabled by env");
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return;
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}
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let mut enc = NvencCudaEncoder::open(
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Codec::H265,
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PixelFormat::X2Rgb10,
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W,
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H,
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60,
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8_000_000,
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true,
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10,
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ChromaFormat::Yuv420,
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true, // cursor_blend: bring up the Vulkan slot ring + the 10-bit blend
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)
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.expect("open NVENC CUDA session");
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let cursor = |serial: u64, x: i32, y: i32| pf_frame::CursorOverlay {
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x,
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y,
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w: 32,
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h: 32,
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rgba: std::sync::Arc::new(vec![0xFF; 32 * 32 * 4]),
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serial,
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hot_x: 0,
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hot_y: 0,
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visible: true,
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};
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let mut aus = 0usize;
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for i in 0..6u32 {
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let mut frame = rgb10_frame(W, H, i);
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// Bitmap serial flips at frame 3 (upload quiesce over in-flight ordered blends); the
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// position moves every frame (push-constant path) — same shape as the 8-bit twin.
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frame.cursor = Some(cursor(
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if i < 3 { 1 } else { 2 },
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40 + i as i32 * 9,
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60 + i as i32 * 5,
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));
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enc.submit_indexed(&frame, i).expect("submit");
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while let Some(au) = enc.poll().expect("poll") {
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assert!(!au.data.is_empty(), "empty AU");
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aus += 1;
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}
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}
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enc.flush().ok();
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assert!(aus > 0, "no AUs produced");
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assert_eq!(enc.bit_depth, 10, "must be a 10-bit session");
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assert_eq!(
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slot_fmt_of(enc.buffer_fmt),
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SlotFormat::X2Rgb10,
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"the blend must target the 10-bit packed slot layout, not the 8-bit one"
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);
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assert!(
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enc.caps().blends_cursor,
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"the direct-SDK path must still report a cursor blend at 10-bit"
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);
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println!("nvenc_cuda HDR10 cursor blend: {aus} AUs, slot fmt X2Rgb10");
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}
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/// ON-HARDWARE (RTX box `.21`): the 4:4:4 path — a planar-YUV444 `DeviceBuffer` through an HEVC
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/// FREXT (chromaFormatIDC=3) session, exercising the stacked-plane input surface + copy that NV12
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/// doesn't. Asserts AUs come out and `caps().chroma_444` reports true (the GPU supports it). Run:
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