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The Windows host capped at ~60 fps with 35-40 ms latency on a GPU-heavy game: the per-frame capture→encode path shared the 3D engine with the game and got scheduled behind it. Rework to minimize 3D-engine work per frame: - VideoConverter (D3D11 video processor): capture → NVENC-native NV12/P010 so NVENC skips its internal RGB→YUV (a 3D/compute step). Wired into both DDA (dxgi.rs) and WGC (wgc.rs). New PixelFormat::Nv12/P010 + NVENC YUV input. - GPU scheduling hardening (Apollo-style): D3DKMTSetProcessSchedulingPriorityClass HIGH, absolute SetGPUThreadPriority, SetMaximumFrameLatency(1). - WGC SDR zero-copy (hold pool frames; no CopyResource). DDA keeps a fast CopyResource to decouple its single-frame acquire/release from the async convert. - Pipelined helper encode loop (PUNKTFUNK_ENCODE_DEPTH, default 1) + perf split (cap_wait / encode / write). Live on the RTX 4090: hard 60 fps ceiling removed (now scene-scaling 40-200+), latency much reduced. Residual cap in GPU-pinned scenes is the irreducible RGB→YUV convert (no fixed-function unit on NVIDIA — VideoProcessing engine reads 0%) waiting behind an uncapped game under WDDM context time-slicing; Linux avoids it via gamescope capping the game to the display refresh. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
52 lines
2.3 KiB
Rust
52 lines
2.3 KiB
Rust
//! Zero-copy capture→encode (plan §9): the PipeWire dmabuf is imported into CUDA via EGL and
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//! handed straight to NVENC, eliminating the per-frame CPU copies (at 5K the CPU-copy path
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//! moves ~3.5 GB/s). Opt in with `PUNKTFUNK_ZEROCOPY=1`; the CPU-copy path stays the default and
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//! the runtime fallback (foreign-allocator / no-dmabuf / import failure).
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//!
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//! Pieces: [`cuda`] (driver-API FFI + the shared `CUcontext` + device buffers), [`egl`] (the
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//! headless EGLDisplay + dmabuf→`EGLImage`→CUDA import). The encoder's CUDA-frame path lives in
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//! `encode/linux.rs`; the dmabuf negotiation lives in `capture/linux.rs`.
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pub mod cuda;
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pub mod egl;
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pub mod vulkan;
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pub use cuda::DeviceBuffer;
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pub use egl::{DmabufPlane, EglImporter};
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/// Whether the zero-copy path is opted in (`PUNKTFUNK_ZEROCOPY` truthy).
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pub fn enabled() -> bool {
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std::env::var("PUNKTFUNK_ZEROCOPY")
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.map(|v| matches!(v.trim(), "1" | "true" | "yes" | "on"))
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.unwrap_or(false)
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}
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/// DRM FourCC for a packed 32-bit format name (little-endian, e.g. `b"XR24"`).
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const fn fourcc(c: &[u8; 4]) -> u32 {
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(c[0] as u32) | ((c[1] as u32) << 8) | ((c[2] as u32) << 16) | ((c[3] as u32) << 24)
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}
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/// Map a SPA/our [`crate::capture::PixelFormat`] to the DRM FourCC EGL expects for import.
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/// SPA byte order `BGRx` ⇒ DRM `XRGB8888` (memory B,G,R,X), etc.
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pub fn drm_fourcc(format: crate::capture::PixelFormat) -> Option<u32> {
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use crate::capture::PixelFormat::*;
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Some(match format {
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Bgrx => fourcc(b"XR24"), // DRM_FORMAT_XRGB8888
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Bgra => fourcc(b"AR24"), // DRM_FORMAT_ARGB8888
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Rgbx => fourcc(b"XB24"), // DRM_FORMAT_XBGR8888
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Rgba => fourcc(b"AB24"), // DRM_FORMAT_ABGR8888
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// 24-bit packed RGB/BGR have no straightforward dmabuf import here; use the CPU path.
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// Rgb10a2/Nv12/P010 are the Windows HDR / video-processor formats — never produced on Linux.
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Rgb | Bgr | Rgb10a2 | Nv12 | P010 => return None,
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})
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}
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/// Standalone probe (the `zerocopy-probe` subcommand): initialize the EGL importer + CUDA
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/// context and report. De-risks the FFI/linking/GPU-access without needing a capture session.
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pub fn probe() -> anyhow::Result<()> {
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let _importer = EglImporter::new()?;
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let ctx = cuda::context()?;
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tracing::info!(cuda_ctx = ?ctx, "zero-copy probe OK — EGL display + CUDA context initialized");
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Ok(())
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}
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