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The Windows host capped at ~60 fps with 35-40 ms latency on a GPU-heavy game: the per-frame capture→encode path shared the 3D engine with the game and got scheduled behind it. Rework to minimize 3D-engine work per frame: - VideoConverter (D3D11 video processor): capture → NVENC-native NV12/P010 so NVENC skips its internal RGB→YUV (a 3D/compute step). Wired into both DDA (dxgi.rs) and WGC (wgc.rs). New PixelFormat::Nv12/P010 + NVENC YUV input. - GPU scheduling hardening (Apollo-style): D3DKMTSetProcessSchedulingPriorityClass HIGH, absolute SetGPUThreadPriority, SetMaximumFrameLatency(1). - WGC SDR zero-copy (hold pool frames; no CopyResource). DDA keeps a fast CopyResource to decouple its single-frame acquire/release from the async convert. - Pipelined helper encode loop (PUNKTFUNK_ENCODE_DEPTH, default 1) + perf split (cap_wait / encode / write). Live on the RTX 4090: hard 60 fps ceiling removed (now scene-scaling 40-200+), latency much reduced. Residual cap in GPU-pinned scenes is the irreducible RGB→YUV convert (no fixed-function unit on NVIDIA — VideoProcessing engine reads 0%) waiting behind an uncapped game under WDDM context time-slicing; Linux avoids it via gamescope capping the game to the display refresh. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
443 lines
19 KiB
Rust
443 lines
19 KiB
Rust
//! NVENC encoder via `ffmpeg-next` (binds the system FFmpeg — `ffmpeg-sys-next` auto-detects the
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//! installed version, so this builds against FFmpeg 7.x/libavcodec 61 *or* 8.x/libavcodec 62;
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//! validated live on Ubuntu 26.04 (FFmpeg 8) and Bazzite F43 (FFmpeg 7.1)).
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//!
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//! Input is a packed RGB/BGR CPU frame; `*_nvenc` accepts `rgb0`/`bgr0`/`rgba`/`bgra`
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//! directly and does the RGB→YUV conversion on the GPU, so the host stays off the
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//! colour-conversion path. The portal commonly negotiates packed 24-bit `RGB`, which NVENC
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//! does *not* accept — we expand it to `rgb0` (one padding byte/pixel, no colour math).
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//! The encoder is opened *without* a global header so VPS/SPS/PPS are emitted in-band on
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//! every IDR — the output is both a playable raw Annex-B stream and self-contained AUs.
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use super::{Codec, EncodedFrame, Encoder};
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use crate::capture::{CapturedFrame, FramePayload, PixelFormat};
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use anyhow::{anyhow, bail, Context, Result};
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use ffmpeg::format::Pixel;
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use ffmpeg::util::frame::Video as VideoFrame;
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use ffmpeg::{codec, encoder, Dictionary, Packet, Rational};
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use ffmpeg_next as ffmpeg;
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use std::os::raw::c_int;
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use ffmpeg::ffi; // = ffmpeg_sys_next
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/// `AVCUDADeviceContext` (libavutil/hwcontext_cuda.h) — not in the ffmpeg-sys bindings (the
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/// crate doesn't allowlist that header), so mirror its stable 3-pointer layout. We set the
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/// first field to *our* `CUcontext` so NVENC shares the context the EGL importer maps into.
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#[repr(C)]
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struct AVCUDADeviceContext {
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cuda_ctx: *mut std::ffi::c_void, // CUcontext
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stream: *mut std::ffi::c_void, // CUstream (null = default)
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internal: *mut std::ffi::c_void, // filled by ctx_init
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}
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/// CUDA hardware-frame contexts that wrap our shared `CUcontext`, so `hevc_nvenc` reads the
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/// imported device buffer directly. Owns two `AVBufferRef`s, unref'd on drop.
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struct CudaHw {
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device_ref: *mut ffi::AVBufferRef,
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frames_ref: *mut ffi::AVBufferRef,
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}
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impl CudaHw {
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/// Build a CUDA hwdevice wrapping `cu_ctx` and a frames pool (`sw_format` = `pixel`).
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unsafe fn new(cu_ctx: *mut std::ffi::c_void, sw_format: Pixel, w: u32, h: u32) -> Result<Self> {
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let mut device_ref = ffi::av_hwdevice_ctx_alloc(ffi::AVHWDeviceType::AV_HWDEVICE_TYPE_CUDA);
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if device_ref.is_null() {
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bail!("av_hwdevice_ctx_alloc(CUDA) failed");
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}
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let dev_ctx = (*device_ref).data as *mut ffi::AVHWDeviceContext;
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let cu = (*dev_ctx).hwctx as *mut AVCUDADeviceContext;
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(*cu).cuda_ctx = cu_ctx; // share the importer's context
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let r = ffi::av_hwdevice_ctx_init(device_ref);
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if r < 0 {
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ffi::av_buffer_unref(&mut device_ref);
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bail!("av_hwdevice_ctx_init failed ({r})");
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}
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let mut frames_ref = ffi::av_hwframe_ctx_alloc(device_ref);
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if frames_ref.is_null() {
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ffi::av_buffer_unref(&mut device_ref);
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bail!("av_hwframe_ctx_alloc failed");
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}
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let fc = (*frames_ref).data as *mut ffi::AVHWFramesContext;
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(*fc).format = ffi::AVPixelFormat::AV_PIX_FMT_CUDA;
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(*fc).sw_format = pixel_to_av(sw_format);
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(*fc).width = w as c_int;
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(*fc).height = h as c_int;
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(*fc).initial_pool_size = 0; // we supply the device pointers
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let r = ffi::av_hwframe_ctx_init(frames_ref);
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if r < 0 {
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ffi::av_buffer_unref(&mut frames_ref);
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ffi::av_buffer_unref(&mut device_ref);
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bail!("av_hwframe_ctx_init failed ({r})");
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}
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Ok(CudaHw {
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device_ref,
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frames_ref,
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})
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}
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}
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impl Drop for CudaHw {
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fn drop(&mut self) {
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unsafe {
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ffi::av_buffer_unref(&mut self.frames_ref);
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ffi::av_buffer_unref(&mut self.device_ref);
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}
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}
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}
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/// `ffmpeg::format::Pixel` → raw `AVPixelFormat`.
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fn pixel_to_av(p: Pixel) -> ffi::AVPixelFormat {
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// `Pixel` is `#[repr(i32)]`-compatible with `AVPixelFormat` (the bindgen enum) via this
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// documented conversion in ffmpeg-next.
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ffi::AVPixelFormat::from(p)
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}
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/// Map a captured layout to the NVENC input pixel format, and whether a 3→4 byte expand is
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/// needed (packed RGB/BGR have no padding byte; the NVENC `*0` formats do).
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fn nvenc_input(format: PixelFormat) -> (Pixel, bool) {
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match format {
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PixelFormat::Bgrx => (Pixel::BGRZ, false), // bgr0
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PixelFormat::Rgbx => (Pixel::RGBZ, false), // rgb0
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PixelFormat::Bgra => (Pixel::BGRA, false),
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PixelFormat::Rgba => (Pixel::RGBA, false),
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PixelFormat::Rgb => (Pixel::RGBZ, true), // RGB -> rgb0
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PixelFormat::Bgr => (Pixel::BGRZ, true), // BGR -> bgr0
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// Rgb10a2 (HDR) and NV12/P010 (the Windows video-processor YUV outputs) are produced only by
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// the Windows capture/encode paths; the Linux capturer never emits them. Map to BGRA so the
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// match is exhaustive — unreachable here.
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PixelFormat::Rgb10a2 | PixelFormat::Nv12 | PixelFormat::P010 => (Pixel::BGRA, false),
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}
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}
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pub struct NvencEncoder {
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enc: encoder::video::Encoder,
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/// Reusable 4-bpp CPU input frame (CPU path only; `None` for the zero-copy/CUDA path).
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/// Mutating it in place across frames is sound only because the encoder is opened with
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/// `delay=0`/`bf=0`/`max_b_frames=0` and the caller drains `poll()` after each `submit`,
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/// so libavcodec holds no reference to the previous frame's buffer when we overwrite it.
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frame: Option<VideoFrame>,
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/// Zero-copy path: CUDA hwdevice/hwframes contexts (the encoder takes `AV_PIX_FMT_CUDA`).
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cuda: Option<CudaHw>,
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src_format: PixelFormat,
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expand: bool,
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width: u32,
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height: u32,
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fps: u32,
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/// Monotonic presentation index, in `1/fps` time-base units.
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frame_idx: i64,
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/// Force the next submitted frame to be an IDR (set by [`request_keyframe`]).
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force_kf: bool,
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}
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// `CudaHw` holds raw `AVBufferRef`s; the encoder lives on a single thread. The CPU encoder is
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// already `Send` via ffmpeg-next; assert it for the CUDA fields too.
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unsafe impl Send for NvencEncoder {}
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impl NvencEncoder {
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#[allow(clippy::too_many_arguments)]
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pub fn open(
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codec: Codec,
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format: PixelFormat,
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width: u32,
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height: u32,
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fps: u32,
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bitrate_bps: u64,
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cuda: bool,
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bit_depth: u8,
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) -> Result<Self> {
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// TODO(hdr): Linux 10-bit parity. Unlike the Windows raw-SDK path (which upconverts 8-bit
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// ARGB → Main10 via pixelBitDepthMinus8), libavcodec hevc_nvenc needs a 10-bit input pixel
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// format (p010) for Main10, so it's a bigger change; deferred until a Linux GPU box is
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// available to validate. The Linux host stays 8-bit for now.
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if bit_depth != 8 {
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tracing::warn!(
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bit_depth,
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"Linux NVENC 10-bit not yet wired — encoding 8-bit"
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);
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}
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ffmpeg::init().context("ffmpeg init")?;
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if std::env::var_os("PUNKTFUNK_FFMPEG_DEBUG").is_some() {
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unsafe { ffi::av_log_set_level(48) }; // AV_LOG_DEBUG — surface NVENC hw-frame rejects
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}
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let name = codec.nvenc_name();
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let av_codec = encoder::find_by_name(name)
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.ok_or_else(|| anyhow!("{name} not built into libavcodec"))?;
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let (nvenc_pixel, expand) = nvenc_input(format);
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let mut video = codec::context::Context::new_with_codec(av_codec)
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.encoder()
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.video()
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.context("alloc video encoder")?;
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video.set_width(width);
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video.set_height(height);
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video.set_format(nvenc_pixel); // NVENC converts RGB→YUV internally
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video.set_time_base(Rational(1, fps as i32));
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video.set_frame_rate(Some(Rational(fps as i32, 1)));
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video.set_bit_rate(bitrate_bps as usize);
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video.set_max_bit_rate(bitrate_bps as usize);
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// VBV/HRD buffer — bound the SIZE of any single frame. Under CBR with no buffer set, NVENC
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// uses a loose default VBV, so a high-motion P-frame is allowed to balloon to many times the
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// average; those extra packets overflow the bounded send queue + kernel socket buffer and
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// get dropped, which the client sees as framedrops/jitter (and, on the infinite-GOP path, as
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// old/stale frames flashing until the next RFI). A tight ~1-frame buffer makes the encoder
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// hold frame size roughly constant and absorb motion as a momentary QP (quality) dip instead
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// — the trade we want. Default = 1 frame of bits (bitrate/fps); PUNKTFUNK_VBV_FRAMES tunes it
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// (larger = better motion quality but bigger per-frame bursts).
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let vbv_frames = std::env::var("PUNKTFUNK_VBV_FRAMES")
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.ok()
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.and_then(|s| s.parse::<f32>().ok())
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.filter(|v| v.is_finite() && *v > 0.0)
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.unwrap_or(1.0);
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let vbv_bits = ((bitrate_bps as f64 / fps.max(1) as f64) * vbv_frames as f64)
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.clamp(1.0, i32::MAX as f64);
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unsafe {
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(*video.as_mut_ptr()).rc_buffer_size = vbv_bits as i32;
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}
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video.set_max_b_frames(0);
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// Infinite GOP — NO periodic IDR. A keyframe at 5120x1440 is ~20-40x a P-frame, so a
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// periodic IDR is a recurring multi-millisecond encode+packetize+send spike — the ~2s
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// "freeze". NVENC emits one IDR at stream start, then P-frames only; `forced-idr` (below)
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// turns a client recovery request (RFI, via `request_keyframe`) into an IDR on demand.
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// This is the Moonlight/Sunshine low-latency model.
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unsafe {
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(*video.as_mut_ptr()).gop_size = -1;
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}
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// For the zero-copy path, take CUDA surfaces: wrap the shared CUcontext in CUDA
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// hwdevice/hwframes contexts and set `pix_fmt = CUDA` on the raw encoder context
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// *before* open (NVENC derives the device from `hw_frames_ctx`).
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let cuda_hw = if cuda {
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let cu_ctx = crate::zerocopy::cuda::context().context("shared CUDA context")?;
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let hw = unsafe { CudaHw::new(cu_ctx, nvenc_pixel, width, height)? };
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unsafe {
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let raw = video.as_mut_ptr();
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(*raw).pix_fmt = ffi::AVPixelFormat::AV_PIX_FMT_CUDA;
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(*raw).hw_device_ctx = ffi::av_buffer_ref(hw.device_ref);
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(*raw).hw_frames_ctx = ffi::av_buffer_ref(hw.frames_ref);
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}
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Some(hw)
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} else {
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None
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};
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// Low-latency NVENC tuning (plan §7 / linux-setup doc).
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let mut opts = Dictionary::new();
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opts.set("preset", "p1"); // fastest
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opts.set("tune", "ull"); // ultra-low-latency
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opts.set("rc", "cbr");
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opts.set("bf", "0");
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opts.set("delay", "0");
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opts.set("forced-idr", "1"); // RFI/request_keyframe → real IDR under the infinite GOP
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// Split-frame encode across both NVENC engines (GB203 has 2) when the pixel rate exceeds
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// a single engine's HEVC capacity (~1 Gpix/s); e.g. 5120x1440@240 = 1.77 Gpix/s needs it,
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// @120 = 0.88 Gpix/s does not. HEVC/AV1 only (not H.264). AUTO won't engage below ~2112px
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// height, so we force `2`; below the threshold we leave it AUTO (split costs ~2% BD-rate).
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// Output is standard HEVC — transparent to the client. Override with PUNKTFUNK_SPLIT_ENCODE.
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let pix_rate = width as u64 * height as u64 * fps as u64;
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let split = std::env::var("PUNKTFUNK_SPLIT_ENCODE").ok();
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match split.as_deref() {
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Some(mode) => opts.set("split_encode_mode", mode),
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None if matches!(codec, Codec::H265 | Codec::Av1) && pix_rate > 1_000_000_000 => {
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opts.set("split_encode_mode", "2");
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tracing::info!(
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pix_rate,
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"NVENC: forcing 2-way split encode (high pixel rate)"
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);
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}
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None => {}
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}
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let enc = video
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.open_with(opts)
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.with_context(|| format!("open {name} ({width}x{height}@{fps}, {bitrate_bps} bps)"))?;
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let frame = if cuda {
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None
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} else {
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Some(VideoFrame::new(nvenc_pixel, width, height))
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};
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Ok(NvencEncoder {
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enc,
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frame,
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cuda: cuda_hw,
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src_format: format,
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expand,
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width,
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height,
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fps,
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frame_idx: 0,
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force_kf: false,
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})
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}
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}
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impl Encoder for NvencEncoder {
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fn submit(&mut self, captured: &CapturedFrame) -> Result<()> {
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anyhow::ensure!(
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captured.width == self.width && captured.height == self.height,
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"captured frame {}x{} != encoder {}x{}",
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captured.width,
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captured.height,
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self.width,
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self.height
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);
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let pts = self.frame_idx;
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self.frame_idx += 1;
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// Force an IDR when requested (client RFI); otherwise let NVENC pick (GOP/P-frame).
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let idr = self.force_kf;
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self.force_kf = false;
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match &captured.payload {
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FramePayload::Cuda(buf) => self.submit_cuda(buf, pts, idr),
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FramePayload::Cpu(bytes) => self.submit_cpu(bytes, captured.format, pts, idr),
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}
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}
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fn request_keyframe(&mut self) {
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self.force_kf = true;
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}
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fn poll(&mut self) -> Result<Option<EncodedFrame>> {
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let mut pkt = Packet::empty();
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match self.enc.receive_packet(&mut pkt) {
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Ok(()) => {
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let data = pkt.data().map(|d| d.to_vec()).unwrap_or_default();
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let pts = pkt.pts().unwrap_or(0).max(0) as u64;
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let pts_ns = pts * 1_000_000_000 / self.fps as u64;
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Ok(Some(EncodedFrame {
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data,
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pts_ns,
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keyframe: pkt.is_key(),
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}))
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}
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// No packet ready yet (need another input frame).
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Err(ffmpeg::Error::Other { errno })
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if errno == ffmpeg::util::error::EAGAIN
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|| errno == ffmpeg::util::error::EWOULDBLOCK =>
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{
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Ok(None)
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}
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// Fully drained after flush().
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Err(ffmpeg::Error::Eof) => Ok(None),
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Err(e) => Err(e).context("receive_packet"),
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}
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}
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fn flush(&mut self) -> Result<()> {
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self.enc.send_eof().context("send_eof")?;
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Ok(())
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}
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}
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impl NvencEncoder {
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/// CPU path: expand/copy the packed RGB/BGR bytes into the reusable 4-bpp frame, then send.
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fn submit_cpu(&mut self, bytes: &[u8], format: PixelFormat, pts: i64, idr: bool) -> Result<()> {
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anyhow::ensure!(
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format == self.src_format,
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"captured format {:?} != encoder source {:?}",
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format,
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self.src_format
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);
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let w = self.width as usize;
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let h = self.height as usize;
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let src_bpp = self.src_format.bytes_per_pixel();
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let src_row = w * src_bpp;
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anyhow::ensure!(
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bytes.len() >= src_row * h,
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"captured buffer {} bytes < required {}",
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bytes.len(),
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src_row * h
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);
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let frame = self
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.frame
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.as_mut()
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.context("CPU frame missing (encoder opened in CUDA mode)")?;
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let stride = frame.stride(0); // dst is 4-bpp, aligned
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let dst = frame.data_mut(0);
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if self.expand {
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// packed 3-bpp RGB/BGR → 4-bpp *0 (copy 3 bytes, zero the pad byte)
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for y in 0..h {
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let s = &bytes[y * src_row..y * src_row + src_row];
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let drow = &mut dst[y * stride..y * stride + w * 4];
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for x in 0..w {
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drow[x * 4..x * 4 + 3].copy_from_slice(&s[x * 3..x * 3 + 3]);
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drow[x * 4 + 3] = 0;
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}
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}
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} else {
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// 4-bpp → 4-bpp, honoring the (possibly larger) dst stride
|
|
for y in 0..h {
|
|
dst[y * stride..y * stride + src_row]
|
|
.copy_from_slice(&bytes[y * src_row..y * src_row + src_row]);
|
|
}
|
|
}
|
|
frame.set_pts(Some(pts));
|
|
frame.set_kind(if idr {
|
|
ffmpeg::picture::Type::I
|
|
} else {
|
|
ffmpeg::picture::Type::None
|
|
});
|
|
self.enc.send_frame(frame).context("send_frame")?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Zero-copy path: hand the imported CUDA device buffer to NVENC with no CPU touch.
|
|
///
|
|
/// We take a *pooled* surface from the CUDA hwframes context (`av_hwframe_get_buffer`) and
|
|
/// device→device-copy our imported buffer into it, rather than wrapping our own pointer in a
|
|
/// bare frame. Two reasons: (1) NVENC's `nvenc_send_frame` ignores frames whose `buf[0]` is
|
|
/// null and the generic encode path's `av_frame_ref` needs a refcounted buffer — a bare
|
|
/// frame is rejected with `EINVAL`; (2) NVENC caches CUDA-resource *registrations* keyed by
|
|
/// device pointer with a bounded table, so a fresh pointer every frame would thrash/overflow
|
|
/// it — the pool recycles a small set of pointers. The extra copy is device-local (~8 MB at
|
|
/// 1080p, sub-millisecond on the GPU) and keeps the host fully off the pixel path.
|
|
fn submit_cuda(
|
|
&mut self,
|
|
buf: &crate::zerocopy::DeviceBuffer,
|
|
pts: i64,
|
|
idr: bool,
|
|
) -> Result<()> {
|
|
let frames_ref = self
|
|
.cuda
|
|
.as_ref()
|
|
.context("CUDA hw context missing (encoder opened in CPU mode)")?
|
|
.frames_ref;
|
|
// The device→device copy below uses our shared context directly; make it current on the
|
|
// encode thread (ffmpeg pushes its own around the pool alloc, so order is fine).
|
|
crate::zerocopy::cuda::make_current().context("CUDA context current (encode thread)")?;
|
|
unsafe {
|
|
let mut f = ffi::av_frame_alloc();
|
|
if f.is_null() {
|
|
bail!("av_frame_alloc failed");
|
|
}
|
|
// Pooled CUDA surface: sets format, width/height, data[0]/linesize[0], buf[0] and
|
|
// hw_frames_ctx. Reused across frames (the pool recycles), keeping NVENC's
|
|
// registration cache warm.
|
|
let r = ffi::av_hwframe_get_buffer(frames_ref, f, 0);
|
|
if r < 0 {
|
|
ffi::av_frame_free(&mut f);
|
|
bail!("av_hwframe_get_buffer(CUDA) failed ({r})");
|
|
}
|
|
let dst_ptr = (*f).data[0] as crate::zerocopy::cuda::CUdeviceptr;
|
|
let dst_pitch = (*f).linesize[0] as usize;
|
|
if let Err(e) = crate::zerocopy::cuda::copy_device_to_device(buf, dst_ptr, dst_pitch) {
|
|
ffi::av_frame_free(&mut f);
|
|
return Err(e).context("copy imported buffer into NVENC surface");
|
|
}
|
|
(*f).pts = pts;
|
|
(*f).pict_type = if idr {
|
|
ffi::AVPictureType::AV_PICTURE_TYPE_I
|
|
} else {
|
|
ffi::AVPictureType::AV_PICTURE_TYPE_NONE
|
|
};
|
|
let r = ffi::avcodec_send_frame(self.enc.as_mut_ptr(), f);
|
|
ffi::av_frame_free(&mut f);
|
|
if r < 0 {
|
|
bail!("avcodec_send_frame(CUDA) failed ({r})");
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|